In current systems, the prevailing paradigm is to view memory as shared, and ensure a consistent view to all processes using hardware-based mechanisms such as cache coherence. However, this approach may not scale as the number of cores in future architectures will continue to increase. An alternative approach has recently been proposed, in which resources are partitioned between processes, and communication is allowed through explicit message passing. In this view, essential shared state is replicated in order to provide processes with faster access to locally stored copies. The consistency of the replicas is ensured through a message-passing agreement protocol. We have previously experimented with such protocols on x86 machines, where the messaging layer was implemented in software. While the protocols show good scalability, the performance of the software-based message passing does not match that of the hardware-based cache coherence. However, certain new architectures (such as Tilera) provide hardware implementations of message passing, with latencies similar to those of the cache coherence. In this project, the student is expected to port the existing protocols to the Tilera architecture: replace the software-based message passing with Tilera's hardware version. All implementations will be in C.

Responsible: Tudor David

Faculty/laboratory: IC/LPD

Semester project for 1 CS or SysCom Master student

Experience with the C programming language required