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+ | ==== Evaluation of Software Transactional Memory Algorithms (Master project) ==== | ||
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+ | === Introduction: Software Transactional Memory === | ||
+ | |||
+ | Multi-core processors are already in laptops, and multi-processor | ||
+ | systems are already outside server rooms. And, in fact, hardware | ||
+ | manufacturers predict that more and more processing units will be packed | ||
+ | into even ordinary computers. The problem is that to exploit the power | ||
+ | of the new systems, we will need to make more applications | ||
+ | multi-threaded. This means that even ordinary programmers will have to | ||
+ | deal with concurrent programming, which is hard and error-prone. | ||
+ | |||
+ | Software transactional memory (STM) is a new method of concurrent | ||
+ | programming that makes implementing scalable, thread-safe data | ||
+ | structures easier than it can be done with lock-based techniques | ||
+ | (monitors, mutexes, etc.). It is said to be multi-threading for the | ||
+ | masses, and the future of concurrent programming. | ||
+ | |||
+ | === Goals of the Project === | ||
+ | |||
+ | The project would consist of: | ||
+ | |||
+ | - Evaluating known STM algorithms using realistic workloads (e.g., the STMBench7 benchmark). | ||
+ | - Discovering limitations and trade-offs of these STM algorithms, as well as of the workloads/benchmarks and (possibly) the multi-processor hardware used in the evaluation. | ||
+ | - Given the results, experimenting with hybrid and adaptive approaches (or other ideas) that could possibly be more suitable for general applications. | ||
+ | |||
+ | === Technical Details === | ||
+ | |||
+ | **Responsible:** [[http://lpd.epfl.ch/kapalka|Michal Kapalka]] (firstname.lastname@epfl.ch) | ||
+ | |||
+ | **Faculty/laboratory:** IC/LPD | ||
+ | |||
+ | **Programming language:** Java and/or C/C++ | ||